The  74F113  offers  individual  J,  K,  Set  and  Clock  inputs. When  the  clock  goes  HIGH  the  inputs  are  enabled  and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flip-flop  will  perform  according  to  the  Truth  Table  as  long  as minimum setup and hold times are observed. Input data is transferred  to  the  outputs  on  the  falling  edge  of  the  clock pulse.

Features :-

• Asynchronous input: LOW input to SD sets Q to HIGH level Set is independent of clock

Specifications :-

• Input HIGH Voltage : 2.0V
• Input LOW Voltage : 0.8V
• Input Clamp Diode Voltage : -1.2V
• Input High Current : 5.0μA
• Input High Current Breakdown Test : 7.0μA
• Output High Leakage Current : 50μA
• Output Short-Circuit Current : -60 - -150mA
• Power Supply Current : 19mA

Package Includes :-

1 X 74F113 Dual JK Negative Edge-Triggered Flip-Flop IC (74113) DIP-16 Package